LFSR for Pseudorandom number generation
Designed and verified a 64-bit 50MHz Linear Feedback Shift Register that generate random numbers used for public and private key generation of an RSA encryption module.
· Skills developed in Verilog synthesis Design, mapping to FPGA and simulation performed using Quartus and Modelsim.
· Skills developed in Verilog synthesis Design, mapping to FPGA and simulation performed using Quartus and Modelsim.
1 Teammate
