This project stood as the concluding assignment for my Digital Logic Design course, representing the culmination of what I had learned during the semester. The assignment's focal point was to create a Finite State Machine with a unique purpose, which was simulating the functionality of a vending machine. Executing this task required programming in Verilog and implementing the design on a BASYS3 FPGA board.

In essence, this artifact highlights my proficiency in digital logic design, Verilog programming, and hardware implementation. It not only showcases my ability to conceptualize and execute intricate designs in digital hardware but also underscores my practical skills in translating theoretical knowledge into a functional, real-world application. This project also highlights my adaptability in coding languages, as Verilog is not a traditional language and requires a distinct thought process for successful implementation. This experience solidifies my grasp of digital systems and my ability to tackle hands-on challenges.

NOTE: In addition to the main document, which is my final report, I have included a video to display the functioning final product.