This design was part of a challenge to create a functional device using basic logic gates. I created and simulated my design in Xilinx to test the functionality of the logic systems, then migrated the simulation to OrCad PSpice where I could add in the analog components that would create the clock. Once I confirmed the design from the schematic worked properly, I began the board layout using Allegro. This challenged me because I was planning to create the PCB at home and wanted to use as few vias as possible. One redesign after another, I finally created a 2 layer board that used no vias and was ready for me to manufacture. I used a common at-home technique of transferring toner to the board to act as an etch resist, and etched the board in my garage. Finally my board was ready for assembly and I soldered all the components to the board, tested to confirm everything was working, and was very pleased to have a working prototype in about a week.