In this clock driver project, I used the Cadence Design Environment and the Virtuoso Simulation to design and analyze a circuit to optimally drive a load of 16 NOR2 and 16 NOR3 gates.
At first, I characterized the TSMC .18um process using the results from a FO4 circuit. Then, using the technique of logical effort I designed the clock driver to drive the loads, calculated the expected delays from input to output voltages assuming Reqp = 2 Reqn, and averaged the computed values of Cg and Cd for both NMOS and PMOS transistors. Finally, I implemented the top-level schematics and simulated the results. I plotted the waveform at both Vin and Vout and measured the rising and falling delays. Also, I verified that the design is both DRC and LVS clean.