Description
·Planned the design, verification, and synthesis of hardware-based motion estimator using ASIC design principles.
·Implemented modular components of motion estimator in Verilog using digital design principles.
·Verified functionality of components using Synopsys VCS and Synthesized full motion estimator design using Synopsys Design compiler, resulting in a design that meets all timing requirements.
Delivered Physical design with layout and parasitic extraction and post synthesis timing verification
Delivered Timing verification results (both setup and hold time) using PrimeTime after DC and after ICC
Successfully:
1. Completed RTL to GDS design and verification by simulation
2. Met the timing (both setup and hold time) in post layout timing verification
3. Achieved minimum in either of the following metrics: area and/or power
Results show:
Simulation run results (waveforms or equivalent)
Front-end synthesis results with gate level netlist and timing and power reports.
 Synthesis and physical design scripts
 Extracts from View_command.log generated by design_vision, including the results from the read command and timing verification. (If you use
dc_shell, you will have to rerun the script in design_vision in order to obtain this).  Plots from the final design and chip layout.
Skills gained:
ASIC implementation using Synopsys EDA tools.
designing a substantial digital system using the Verilog/Synthesis techniques